1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly to a static semiconductor memory device which can prevent operational failure caused by increase of voltage at a ground voltage line at the time of high speed and low voltage operation.
2. Descriptions of the Prior Art
Memory cells of the static semiconductor memory device can be classified into a CMOS type comprising six transistors and a high-resistance loading type comprising two resistors and four transistors.
The high-resistance loading type memory cell is advantageous in reducing the chip area, but disadvantageous in increasing power consumption. The CMOS type memory cell is advantageous in reducing power consumption, but advantageous in increasing the chip area.
In a conventional static semiconductor memory device, the high-resistance loading type memory cell is used for constructing memory cell arrays to reduce the chip area.
However, since the static semiconductor memory device operates at high speed and at low voltage, the CMOS type memory cell is inevitably used to reduce power consumption.
A technique disclosed in U.S. Pat. No. 5,654,915 entitled "Six (6) Bulk Transistor Static Memory Cell Using Split Word line Architecture" discloses the layout of a CMOS type memory cell to reduce the chip area.
FIG. 1 illustrates the circuit and signal line arrangement of the CMOS type of memory cells disclosed in U.S. Pat. No. 5,654,915.
The CMOS type of memory cell is constructed with two (2) loading transistors P1, P2; two access transistors N1, N4; and two pulldown transistors N2, N3. The two loading transistors P1, P2 are vertically arranged in a rectangular shape. Also, the access transistors N1, N4 and two pulldown transistors N2, N3 are vertically arranged in a rectangular shape.
A split word line WL extends in a horizontal direction, and a supply voltage line VCC, a ground voltage line VSS and a pair of bit lines BL, BLB extends in a vertical direction.
The operation of the CMOS type of memory cells thus constructed will be described below.
A high-level signal is applied to a word line WL to turn on the two access transistors N1, N4. A high-level signal is applied to the bit line BL. A low level signal is applied to the inverted bit line BLB. The high and low level signals are transmitted to the drains of the two access transistors N1, N4. The loading transistor P1 and the pulldown transistor N3 turn on. The high and low level signals are further transmitted to the drains of the access transistors N1, N4. In other words, the signals transmitted through the access transistors N1, N4 are latched by cross-coupled transistors P1, P2 and pulldown transistors N2, N3. The complementary signals present on the bit lines BL, BLB thus are stored in the memory cell.
FIG. 2 illustrates the layout of the memory cell shown in FIG. 1, including an active area 10 constructed with loading transistors and another active area 12 constructed with access transistors and pulldown transistors. Furthermore, reference symbols P1d, P2d, N1d, N2d, N3d, N4d indicate drains of the transistors, reference symbols, P1s, P2s, N1s, N2s, N3s, N4s indicate sources of the transistors, and P1g, P2g, N1g, N2g, N3g, N4g indicate gates of the transistors.
Above mentioned U.S. Pat. No. 5,654,915 discloses the same layout of memory cell as shown in FIG. 2 to improve the structure of the conventional CMOS type of memory cell.
However, there is a problem in the CMOS type memory cell shown in FIG. 2. In detail, if the ground voltage line gets longer to increase its voltage, the margin between the supply voltage level and the ground voltage level decreases during low-voltage operation, thereby potentially causing operational failure in processing the data latched by the memory cell.
Accordingly, a need arises to correct such a problem in any static semiconductor memory device constructed with the conventional CMOS type memory cell as well as in the static semiconductor memory device constructed in the layout shown in FIGS. 1 and 2.